In one aspect, the present inventions described and illustrated herein relate to an integrated circuit device having a memory cell array including a plurality of rows and columns, and techniques for controlling and/or operating such a device. More particularly, in one aspect, the present inventions relate to an integrated circuit having memory cell array including a plurality of bit lines and a plurality of bit line segments, wherein a plurality of bit line segments are associated with each bit line, and wherein each bit line segment includes a plurality of memory cells (for example, memory cells having an electrically floating body in which a charge is stored) associated therewith and connected thereto; isolation circuits selectively and responsively couple an associated bit line segment to an associated bit line.
Briefly, with reference to FIG. 1, memory cell array 10 typically includes a plurality of memory cells 12 arranged in a matrix of rows and columns. A row address decoder enables one or more rows to be read by sensing circuitry (for example, a plurality of sense amplifiers). A column decoder, in response to an address, selects one or more of the outputs of the data sensing circuitry.
One type of dynamic random access memory cell is based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662). In this regard, the memory cell may consist of a partially depleted (PD) or a fully depleted (FD) SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of cell is determined by the concentration of charge in the body of the transistor.
With reference to FIGS. 2A, 2B, 2C and 2D, memory cell array 10 may include a plurality of memory cells 12, each consisting of transistor 14 having gate 16, an electrically floating body region 18, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material) or non-conductive region (for example, in bulk-type material). The insulation or non-conductive region may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, and/or a selected bit line(s) 32. The source line (30) is a common node in a typical implementation though it could be similarly decoded. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
As mentioned above, memory cell 12 of memory cell array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, N-channel transistors. (See, FIGS. 3A and 3B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 3A). Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See, FIG. 3B).
Notably, an advantage of the floating body memory cell compared to a more traditional DRAM cell (i.e., one transistor and one capacitor) is that the floating body memory cell does not require an associated capacitor to store charge. This tends to reduce process complexity and provide a smaller memory cell footprint. In this way, the cost of a memory cell array implementing such memory cells is less than conventional memory cell arrays.
Another significant concern in memory cell arrays is power consumption. The need for products with reduced power consumption is particularly acute due to proliferation of battery powered products. With the floating body memory, one source of power consumption is the power consumed during refresh operations. A refresh operation involves reading the state of a cell and re-writing that cell to the state that was read. This may be necessary as a result of gradual loss of charge over time in the floating body. The rate of charge loss increases in a floating body array when disturb voltages are applied to the nodes of a given cell. These disturb voltages occur in an array when reads and writes are made to rows in a shared array. The unselected row remains with its gate off, but its drain nodes are “exposed” to changing voltages due to the voltages applied to the shared bit line.
Notably, the above mentioned disturb voltage tends to reduce the refresh interval necessary to maintain stored data and thus, increase the power consumption required to maintain stored data.